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general description the max3420e contains the digital logic and analog circuitry necessary to implement a full-speed usb peripheral compliant to usb specification rev 2.0. a built-in full-speed transceiver features ?5kv esd pro- tection and programmable usb connect and discon- nect. an internal serial-interface engine (sie) handles low-level usb protocol details such as error checking and bus retries. the max3420e operates using a regis- ter set accessed by an spi interface that operates up to 26mhz. any spi master (microprocessor, asic, dsp, etc.) can add usb functionality using the simple 3- or 4-wire spi interface. internal level translators allow the spi interface to run at a system voltage between 1.71v and 3.6v. usb timed operations are done inside the max3420e with inter- rupts provided at completion so an spi master does not need timers to meet usb timing requirements. the max3420e includes four general-purpose inputs and outputs so any microprocessor that uses i/o pins to implement the spi interface can reclaim the i/o pins and gain additional ones. the max3420e operates over the extended -40? to +85? temperature range and is available in a 32-pin lqfp package (7mm x 7mm) and a space-saving 24- pin tqfn package (4mm x 4mm). applications features ? microprocessor-independent usb solution ? complies with usb specification revision 2.0 (full-speed operation) ? integrated full-speed usb transceiver ? firmware/hardware control of an internal d+ pullup resistor ? programmable 3- or 4-wire 26mhz spi interface ? level translators and v l input allow independent system interface voltage ? internal comparator detects v bus for self-powered applications ? esd protection on d+, d-, and vbcomp ? interrupt output pin (level or programmable edge) allows polled or interrupt-driven spi interface ? intelligent usb serial-interface engine (sie) automatically handles usb flow control and double buffering handles low-level usb signaling details contains timers for usb time-sensitive operations so spi master does not need to time events ? built-in endpoint fifos ep0: control (64 bytes) ep1: out, bulk or interrupt, 2 x 64 bytes (double-buffered) ep2: in, bulk or interrupt, 2 x 64 bytes (double-buffered) ep3: in, bulk or interrupt (64 bytes) ? double-buffered data endpoints increase throughput by allowing the spi master to transfer data concurrently with usb transfers over the same endpoint ? setup data has its own 8-byte fifo, simplifying firmware ? four general-purpose inputs and four general- purpose outputs ? space-saving lqfp and tqfn packages max3420e usb peripheral controller with spi interface ________________________________________________________________ maxim integrated products 1 19-3781; rev 2; 6/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available cell phones pc peripherals microprocessors and dsps custom usb devices cameras desktop routers plcs set-top boxes pdas mp3 players instrumentation part temp range pin- package package code m ax 3420e e tg+ - 40c to + 85c 24 tqfn - e p * 4m m x 4m m x 0.8m m t2444- 4 m ax 3420e e c j+ - 40c to + 85c 32 lqfp 7m m x 7m m x 1.4m m c 32- 1 ordering information +denotes lead-free package. * ep = exposed paddle, connected to ground. spi is a trademark of motorola, inc.
the max3420e connects to any microprocessor using 3 or 4 interface pins (figure 1). on a simple micro- processor without spi hardware, these can be bit- banged general-purpose i/o pins. four gpin and four gpout pins on the max3420e more than replace the ? pins necessary to implement the interface. although the max3420e spi hardware includes separate data-in (mosi, (master-out, slave-in)) and data-out (miso, (master-in, slave-out)) pins, the spi interface can also be configured for the mosi pin to carry bidirectional data, saving an interface pin. this is referred to as half- duplex mode. two max3420e features make it easy to connect to large, fast chips such as asics and dsps (see figure 2). first, the spi interface can be clocked up to 26mhz. second, a v l pin and internal level translators allow running the system interface at a lower voltage than the 3.3v required for v cc . the max3420e provides an ideal method for electrically isolating a usb interface (figure 3). usb employs flow control in which the max3420e automatically answers host requests with a nak handshake, until the micro- processor completes its data-transfer operations over the spi port. this means that the spi interface can run at any frequency up to 26mhz. therefore, the designer is free to choose the interface operating frequency and to make opto-isolator choices optimized for cost or per- formance. max3420e usb peripheral controller with spi interface 2 _______________________________________________________________________________________ typical application circuits 3.3v regulator spi 3, 4 int usb p max3420e 3.3v regulator power rail asic, dsp, etc. spi 3, 4 int max3420e usb figure 2. the max3420e connected to a large chip 3.3v regulator miso local gnd local power int max3420e sclk mosi ss micro asic dsp i s o l a t o r s usb figure 3. optical isolation of usb using the max3420e figure 1. the max3420e connects to any microprocessor using 3 or 4 interface pins
max3420e usb peripheral controller with spi interface _______________________________________________________________________________________ 3 functional diagram gpin3 r gpin 1v to 3v vbcomp d- d+ v cc gpin2 gpin1 gpin0 gpout3 gpout2 gpout1 gpout0 vbus comp ss miso sclk int spi slave interface usb sie (serial-interface engine) full-speed usb transceiver reset logic 1.5k internal por res xi v l xo power down osc and pll 4x 48mhz esd protection esd protection gpx vbus_det operate sof busact mux 0123 mosi vbus_det endpoint buffers max3420e gnd
max3420e usb peripheral controller with spi interface 4 _______________________________________________________________________________________ pin description pin tqfn lqfp name input/ output function 11 gpout0 22 gpout1 output g ener al - p ur p ose p ush- p ul l o utp uts. g p ou t3g p ou t0 l og i c l evel s ar e r efer enced to the vol tag e on v l . the s p i m aster contr ol s the g p ou t3gp ou t0 states b y w r i ti ng to b i t 3 thr oug h b i t 0 of the iop in s ( r20) r eg i ster . 3 3, 4 v l input level-translator reference voltage. connect v l to the system? 1.71v to 3.6v logic-level power supply. bypass v l to ground with a 0.1? capacitor as close to the v l pin as possible. 4, 14 5, 6, 18, 19 gnd input ground 57 gpout2 68 gpout3 output gener al - p ur p ose p ush- p ul l o utp uts. gp ou t3gp o u t0 l og i c l evel s ar e r efer enced to the vol tag e on v l . the s p i m aster contr ol s the gp o u t3gp ou t0 states b y w r i ti ng to b i t 3 thr oug h b i t 0 of the iop in s ( r20) r eg i ster . 710 res input device reset. drive res low to clear all of the internal registers except for pinctl (r17), usbctl (r15), and spi logic. see the device reset section for a description of resets available on the max3420e. note: the max3420e is internally reset if either v cc of v l is not present. the register file is not accessible under these conditions. 8 11 sclk input spi serial-clock input. an external spi master supplies this clock with frequencies up to 26mhz. the logic level is referenced to the voltage on v l . data is clocked into the spi slave interface on the positive edge of sclk. data is clocked out of the spi slave interface on the falling edge of sclk. 912 ss input spi slave-select input. the ss logic level is referenced to the voltage on v l . when ss is driven high, the spi slave interface is not selected and sclk transitions are ignored. an spi transfer begins with a high-to-low ss transition and ends with a low-to-high ss transition. 10 13 miso output spi serial-data output (master-in, slave-out). miso is a push-pull output. miso is tri-stated in half-duplex mode or when ss = 1. the miso logic level is referenced to the voltage on v l . 11 14 mosi input or input/ output spi serial-data input (master-out, slave-in). the logic level on mosi is referenced to the voltage on v l . mosi can also be configured as a bidirectional mosi/miso input and output. 12 15 gpx output general-purpose multiplexed output. the internal max3420e signal that appears on gpx is programmable by writing to the gpxb and gpxa bits of the pinctl (r17) register. gpx indicates one of four signals: operate (00, default), vbus_det (01), busact (10), and sof (11). 13 17 int output inter r up t outp ut. in ed g e m od e, the l og i c l evel on in t i s r efer enced to the vol tag e on v l. in ed g e m od e, in t i s a p ush- p ul l outp ut w i th p r og r am m ab l e p ol ar i ty. in l evel m od e, in t i s op en- d r ai n and acti ve l ow . s et the ie b i t i n the c p u c tl ( r16) r eg i ster to enab l e in t. 15 20 d- input/ output u s b d - s i g nal . c onnect d - to a u s b b connector thr ough a 33 ? 1% ser i es r esi stor .
register description the spi master controls the max3420e by reading and writing 21 registers (table 1). for a complete descrip- tion of register contents, please refer to the ?ax3420e programming guide.?a register access consists of the spi master first writing an spi command byte, followed by reading or writing the contents of the addressed register. all spi transfers are msb first. the command byte contains the register address, a direction bit (read = 0, write = 1), and the ackstat bit (figure 4). the spi master addresses the max3420e registers by writing the binary value of the register number in the reg4 through reg0 bits of the command byte. for example, to access the iopins (r20) register, the reg4 through reg0 bits would be as follows: reg4 = 1, reg3 = 0, reg2 = 1, reg1 = 0, reg0 = 0. the dir (direction) bit determines the direction for the data transfer. dir = 1 means the data byte(s) will be written to the register, and dir = 0 means the data byte(s) will be read from the register. the ackstat bit sets the ackstat bit in the epstalls (r9) register. the spi master sets this bit to indicate that it has finished servicing a control transfer. since the bit is frequently used, having it in the spi command byte improves firmware efficiency. in spi full-duplex mode, the max3420e clocks out eight usb status bits as the command byte is clocked in (figure 5). in half-duplex mode, these status bits are accessed in the normal way, as register bits. max3420e usb peripheral controller with spi interface _______________________________________________________________________________________ 5 pin description (continued) pin tqfn lqfp name input/ output function 16 21 d+ input/ output usb d+ signal. connect d+ to a usb b connector through a 33 ?% series resistor. the 1.5k d+ pullup resistor is internal to the device. 17 22, 23 v cc input usb transceiver power-supply input. connect v cc to a positive 3.3v power supply. bypass v cc to ground with a 1.0? ceramic capacitor as close to the v cc pin as possible. 18 24 vbcomp input v bus comparator input. vbcomp is internally connected to a voltage comparator to allow the spi master to detect (through an interrupt or checking a register bit) the presence or loss of power on v bus . bypass vbcomp to ground with a 1.0? ceramic capacitor. 19 26 xi input crystal oscillator input. connect xi to one side of a parallel resonant 12mhz ?.25% crystal and a capacitor to gnd. xi can also be driven by an external clock referenced to v cc . 20 27 xo output crystal oscillator output. connect xo to the other side of a parallel resonant 12mhz ?.25% crystal and a capacitor to gnd. leave xo unconnected if xi is driven with an external source. 21 29 gpin0 22 30 gpin1 23 31 gpin2 24 32 gpin3 input general-purpose inputs. gpin3?pin0 are connected to v l with internal pullup resistors. gpin3?pin0 logic levels are referenced to the voltage on v l . the spi master samples gpin3?pin0 states by reading bit 7 through bit 4 of the iopins (r20) register. writing to these bits has no effect. 9, 16, 25, 28 n.c. no internal connection ep gnd input exposed paddle on the bottom of the tqfn package. connect ep to gnd. figure 4. spi command byte b7 b6 b5 b4 b3 b2 b1 b0 reg4 reg3 reg2 reg1 reg0 0 dir ackstat figure 5. usb status bits clocked out as first byte of every transfer (full-duplex mode only) b7 b6 b5 b4 b3 b2 b1 b0 suspirq uresirq sudavirq in3bavirq in2bavirq out1davirq out0davirq in0bavirq
max3420e the first five registers (r0?4) access endpoint fifos. to access a fifo, an initial command byte sets the register address and then consecutive reads or writes keep the same register address to access subsequent fifo bytes. the remaining registers (r5?20) control the operation of the max3420e. once a register address above r4 is set in the command byte, successive byte reads or writes in the same spi access cycle ( ss low) increment the register address after every byte read or written. this incrementing operation continues until r20 is accessed. subsequent byte reads or writes continue to access r20. note that this autoincrementing action stops with the next spi cycle, which establishes a new register address. addressing beyond r20 is ignored. the max3420e register map is depicted in table 1. for a complete description of all register contents, please refer to the max3420e programming guide. usb peripheral controller with spi interface 6 _______________________________________________________________________________________ table 1. max3420e register map r eg name b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c r0 ep0 f if o b 7b 6b 5b 4b 3b 2b 1b 0 rs c r1 ep1 o u t f if o b 7b 6b 5b 4b 3b 2b 1b 0 rs c r2 ep2 in f if o b 7b 6b 5b 4b 3b 2b 1b 0 rs c r3 ep3 in f if o b 7b 6b 5b 4b 3b 2b 1b 0 rs c r4 su d f if o b 7b 6b 5b 4b 3b 2b 1b 0 rs c r5 ep0 b c 0b 6b 5b 4b 3b 2b 1b 0 rs c r6 ep1 o u t b c 0b 6b 5b 4b 3b 2b 1b 0 rs c r7 ep2 in b c 0b 6b 5b 4b 3b 2b 1b 0 rs c r8 ep3 in b c 0b 6b 5b 4b 3b 2b 1b 0 rs c r9 epst a l l s 0 ac ks tat s tls tat s tle p 3in s tle p 2in s tle p 1ou ts tle p 0ou ts tle p 0in rs c r10 c l r t o g s e p 3d is ab e p 2d is ab e p 1d is ab c tg e p 3in c tg e p 2in c tg e p 1ou t 00 rs c r11 epi r q 00 s u d av irq in 3bav irq in 2bav irq ou t1d av irq ou t0d av irq in 0bav irq rc r12 epi en 00 s u d av ie in 3bav ie in 2bav ie ou t1d av ie ou t0d av ie in 0bav ie rs c r13 u sb ir q u re s d n irq v bu s irq n ov bu s irq s u s p irq u re s irq bu s ac tirq rwu d n irq os c okirq rc r14 u sb ien u re s d n ie v bu s ie n ov bu s ie s u s p ie u re s ie bu s ac tie rwu d n ie os c okie rs c r15 u sb c t l h os c s te n v bg ate c h ip re s p wrd own c on n e c t s ig rwu 0 0 rs c r16 c pu c t l 000 00 0 0 ie rs c r17 pin c t l e p 3in ak e p 2in ak e p 0in ak fd u p s p iin tle v e l p os in tgp x bgp x a rs c r18 r evisio n 000 00 1 0 0 r r19 f n a d d r 0b 6b 5b 4b 3b 2b 1b 0 r r20 io pin s gp in 3 gp in 2 gp in 1gp in 0 gp o u t3 gp o u t2 gp o u t1 gp o u t0 rs c note: the acc (access) column indicates how the spi master can access the register. r = read, rc = read or clear, rsc = read, set, or clear. writing to an r register (read only) has no effect. writing a 1 to an rc bit (read or clear) clears the bit. writing a zero to an rc bit has no effect.
max3420e usb peripheral controller with spi interface _______________________________________________________________________________________ 7 tqfn max3420e *ep 1234 7 8 9 10 11 * exposed paddle connected to ground 12 24 23 22 21 20 19 56 18 17 16 15 14 13 gpout0 v l gpout1 gpout3 sclk res miso mosi gpx gpin3 gpin2 gpin0 xo xi gpout2 gnd vbcomp d+ v cc d- int gnd gpin1 top view max3420e lqfp top view 32 28 29 30 31 25 26 27 gpin2 gpin1 gpin0 n.c. gpin3 xo xi n.c. 10 13 15 14 16 11 12 9 n.c. sclk res miso ss gpx mosi n.c. 17 18 19 20 21 22 23 v cc 24 vbcomp v cc d+ d- gnd gnd int 2 3 4 5 6 7 8 gpout3 gpout2 gnd gnd v l v l gpout1 1 gpout0 ss + + pin configurations
max3420e usb peripheral controller with spi interface 8 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3v to +3.6v, v l = +1.71v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v cc ......................................................................... -0.3v to +4v v l .............................................................................-0.3v to +4v vbcomp .................................................................-0.3v to +6v d+, d-, xi, xo ............................................-0.3v to (v cc + 0.3v) sclk, mosi, miso, ss , res , gpout3?pout0, gpin3?pin0, gpx, int ..........................-0.3v to (v l + 0.3v) continuous power dissipation (t a = +70?) 24-pin tqfn (derate 20.8mw/? above +70?) .......1667mw 32-pin lqfp (derate 20.7mw/? above +70?)........1653mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc characteristics supply voltage v cc v cc 3.0 3.3 3.6 v logic-core supply and logic- interface voltage v l v l 1.71 3.60 v v cc supply current i cc continuously transmitting on d+ and d- at 12mbps, c l = 50pf on d+ and d- to gnd, connect = 0 15 30 ma v l supply current i l sclk toggling at 20mhz, ss = low, gpin3?pin0 = 0 620ma v cc supply current during idle i ccid d+ = high, d- = low 1.5 5 ma v cc suspend supply current i ccsus connect = 0, pwrdown = 1 33 100 ? v l s usp end s up p l y c urr ent i lsus connect = 0, pwrdown = 1 15 50 a logic-side i/o i load = +5ma, v l < 2.5v v l - 0.45 miso, gpout3?pout0, gpx, int output high voltage v oh i load = +10ma, v l 2.5v v l - 0.4 v i load = -20ma, v l < 2.5v 0.6 miso, gpout3?pout0, gpx, int output low voltage v ol i load = -20ma, v l 2.5v 0.4 v sclk, mosi, gpin3?pin0, ss , res input high voltage v ih 2/3 x v l v sclk, mosi, gpin3?pin0, ss , res input low voltage v il 0.4 v sclk, mosi, ss , res input leakage current i il 1a gp in 3gp in 0 p ul l up resi stor to v l r gpin 10 20 30 k transceiver specifications differential-receiver input sensitivity |v d+ - v d- | 0.2 v differential-receiver common- mode voltage 0.8 2.5 v
max3420e usb peripheral controller with spi interface _______________________________________________________________________________________ 9 electrical characteristics (continued) (v cc = +3v to +3.6v, v l = +1.71v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25 c.) (note 1) parameter symbol conditions min typ max units single-ended receiver input low voltage v il 0.8 v single-ended receiver input high voltage v ih 2.0 v single-ended receiver hysteresis voltage 0.2 v d+, d- input impedance 300 k d+, d- output low voltage v ol r l = 1.5k from d+ to 3.6v 0.3 v d+, d- output high voltage v oh r l = 15k from d+ and d- to gnd 2.8 3.6 v driver output impedance excluding external resistor (note 2) 2 7 11 d+ pullup resistor r ext = 33 1.425 1.5 1.575 k esd protection (d+, d-, vbcomp) human body model 1? ceramic capacitors from vbcomp and v cc to gnd ?5 kv iec61000-4-2 air-gap discharge 1? ceramic capacitors from vbcomp and v cc to gnd ?2 kv iec61000-4-2 contact discharge 1? ceramic capacitors from vbcomp and v cc to gnd ? kv thermal shutdown thermal-shutdown low-to-high +160 ? thermal-shutdown high-to-low +140 ? crystal oscillator specifications (xi, xo) xi input high voltage 2/3 x v c c v cc v xi input low voltage 0.4 v xi input current 10 ? xi, xo input capacitance 3pf vbcomp comparator specifications vbcomp comparator threshold v th 1.0 2.0 3.0 v vbcomp comparator hysteresis v hys 375 mv vbcomp comparator input impedance r in 100 k
max3420e usb peripheral controller with spi interface 10 ______________________________________________________________________________________ note 1: parameters are 100% production tested at t a = +25?, and guaranteed by correlation over temperature. note 2: design guaranteed by bench testing. limits are not production tested. note 3: at v l = 1.71v to 2.5v, derate all of the spi timing characteristics by 50%. not production tested. note 4: the minimum period is derived from spi timing parameters. note 5: time-to-exit suspend is dependent on the crystal used. parameter symbol conditions min typ max units parameter symbol conditions min typ max units usb transmitter timing characteristics d+, d- rise time t rise c l = 50pf, figures 6 and 7 4 20 ns d+, d- fall time t fall c l = 50pf, figures 6 and 7 4 20 ns rise-/fall-time matching c l = 50pf, figures 6 and 7 (note 2) 90 110 % output-signal crossover voltage c l = 50pf, figures 6 and 7 (note 2) 1.3 2.0 v spi bus timing characteristics (v l = 2.5v) (figures 8 and 9) (note 3) v l = 1.71v 77.0 s eri al c l ock ( sc lk) p eri od ( n ote 4) t cp v l = 2.5v 38.4 ns sclk pulse-width high t ch 17 ns sclk pulse-width low t cl 17 ns ss fall to miso valid t css 20 ns ss leading time before the first sclk edge t l 30 ns ss trailing time after the last sclk edge t t 30 ns data-in setup time t ds 5ns data-in hold time t dh 10 ns ss pulse high t csw 200 ns sclk fall to miso propagation delay t do 14.2 ns sclk fall to mosi propagation delay t di 14.2 ns sclk fall to mosi drive t on 3.5 ns ss high to mosi high impedance t off 20 ns suspend timing characteristics time-to-enter suspend pwrdown = 1 to oscillator stop 5 s time-to-exit suspend pwrdown = 1 to 0 to oscokirq (note 5) 3 ms timing characteristics ( v cc = +3v to +3.6v, v l = +1.71v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25 c.) (note 1 )
max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 11 test circuits and timing diagrams figure 6. rise and fall times v ol v oh t rise t fall 90% 10% figure 7. load for d+/d- ac measurements max3420e d+ or d- test point 33 15k c l sclk ss mosi miso t ds t dh t cl t do t ch t t high impedance 8 1 2 9 10 16 t l t css t csw t cp high impedance figure 9. spi bus timing diagram (half-duplex mode, spi mode (0,0)) sclk mosi miso notes: 1) during the first 8 clocks cycles, the mosi pin is high impedance and the spi master drives data onto the mosi pin. setup and hold times are the same as for full-duplex mode. 2) for spi write cycles, the mosi pin continues to be high impedance and the external master continues to drive mosi. 3) for spi read cycles, after the 8th clock-rising edge, the max3420e starts driving the mosi pin after time t on . the external master must turn off its driver to the mosi pin before t on to avoid contention. propagation delays are the same as for the mosi pin in full-duplex mode. t ds t dh t cl t ch t di t off t t ss hi-z 8 1 2 9 10 16 t l t csw t on t cp high impedance high impedance figure 8. spi bus timing diagram (full-duplex mode, spi mode (0,0))
max3420e usb peripheral controller with spi interface 12 ______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, v l = +3.3v, t a = +25?.) detailed description the max3420e contains the digital logic and analog circuitry necessary to implement a full-speed usb peripheral that complies with the usb specification rev 2.0. esd protection of ?5kv is provided on d+, d-, and vbcomp. the max3420e features an internal usb transceiver and an internal 1.5k resistor that connects between d+ and v cc under the control of a register bit (connect). this allows a usb peripheral to control the logical connection to the usb host. any spi master can communicate with the max3420e through the spi slave interface that operates in spi mode (0,0) or (1,1). an spi master accesses the max3420e by reading and writing to internal registers. a typical data transfer con- sists of writing a first byte that sets a register address and direction with additional bytes reading or writing data to the register or internal fifo. the max3420e contains 384 bytes of endpoint buffer memory, implementing the following endpoints: ep0: 64-byte bidirectional control endpoint ep1: 2 x 64-byte double-buffered bulk/int out endpoint ep2: 2 x 64-byte double-buffered bulk/int in endpoint ep3: 64-byte bulk/int in endpoint the choice to use ep1, ep2, ep3 as bulk or inter- rupt endpoints is strictly a function of the endpoint descriptors that the spi master returns to the usb host during enumeration. the max3420e register set and spi interface is optimized to reduce spi traffic. an interrupt output pin, int, notifies the spi master when usb service is required: when a packet arrives, a packet is sent, or the host suspends or resumes bus activity. double-buffered endpoints help sustain bandwidth by allowing data to move concurrently over usb and the spi interface. v cc power the usb transceiver by applying a positive 3.3v supply to v cc . bypass v cc to gnd with a 1.0? ceramic capacitor as close to the v cc pin as possible. v l the max3420e digital core is powered though the v l pin. v l also acts as a reference level for the spi inter- face and all other inputs and outputs. connect v l to the system? logic-level power supply. internal level transla- tors and v l allow the spi interface and all general-pur- pose inputs and outputs to operate at a system voltage between 1.71v and 3.6v. vbcomp the max3420e features a usb v bus detector input, vbcomp. the vbcomp pin can withstand input volt- ages up to 6v. bypass vbcomp to gnd with a 1.0? ceramic capacitor. according to usb specification rev 2.0, a self-powered usb device must not power the 1.5k pullup resistor on d+ if the usb host turns off v bus . vbcomp is internally connected to a voltage comparator so that the spi master can detect the loss of v bus (through an interrupt (int) or checking a bit eye diagram max3420e toc01 4 1 0 -1 01020304050607080 2 3 time (ns) d+ and d- (v)
(novbusirq)) and disconnect the internal 1.5k pullup resistor. if the device using the max3420e is bus powered (through a +3.3v regulator connected to v cc ), the max3420e vbcomp input can be used as a general-purpose input. using vbcomp as a general- purpose input requires a 10k pullup resistor from vbcomp to v l . see the applications information sec- tion for more details about this connection. d+ and d- the internal usb full-speed transceiver is brought out to the bidirectional data pins d+ and d-. these pins are ?5kv esd protected. connect d+ and d- to a usb ??connector through 33 ?% series resistors. a switchable 1.5k pullup resistor is internally connected to d+. according to the usb rev 2.0 specification, a self-powered peripheral must disconnect its 1.5k pullup resistor to d+ in the event that the host turns off bus power. the vbgate bit in the usbctl (r15) regis- ter provides the option for the max3420e internal logic to automatically disconnect the 1.5k resistor on d+. the vbgate and connect bits of usbctl (r15), along with the vbcomp comparator output (vbus_det), control the pullup resistor between v cc and d+, as shown in table 2. note that if vbgate = 1 and vbus_det = 0, the pullup resistor is disconnected regardless of the connect bit setting. xi and xo xi and xo connect an external 12mhz crystal to the internal oscillator circuit. xi is the crystal oscillator input, and xo is the crystal oscillator output. connect one side of an external 12mhz 0.25% parallel reso- nant crystal to xi, and connect xo to the other side. connect load capacitors (20pf max) to ground on both xi and xo. xi can also be driven with an external 12mhz ?.25% clock. if driving xi with an external clock, leave xo unconnected. the external clock must meet the voltage characteristics depicted in the electrical characteristics table. internal logic is single- edge triggered. the external clock should have a nomi- nal 50% duty cycle. res drive res low to put the max3420e into a chip reset. a chip reset sets all registers to their default states, except for pinctl (r17), usbctl (r15), and spi logic. all fifo contents are unknown during chip reset. bring the max3420e out of chip reset by driving res high. the res pulse width can be as short as 200ns. see the device reset section for a description of the resets available on the max3420e. int the max3420e int output pin signals when a usb event occurs that requires the attention of the spi mas- ter. the spi master must set the ie bit in the cpuctl (r16) register to activate int. when the ie bit is cleared, int is inactive (open for level mode, high for negative edge, low for positive edge). int is inactive upon power-up or after a chip reset. the int pin can be a push-pull or open-drain output. set the intlevel bit of the pinctl (r17) register high to program the int output pin to be an active-low level (open-drain output). an external pullup resistor to v l is required for this setting. in level mode, the max3420e drives int low when any of the interrupt flags are set. if multiple interrupts are pending, int goes inactive only when the spi master clears the last active interrupt request bit (figure 10). the posint bit of the pinctl (r17) register has no effect on int in level mode. clear the intlevel bit to program int to be an edge (push-pull output). the active edge is programmable using the posint bit of the pinctl (r17) register. in edge mode, the max3420e produces an edge refer- enced to v l any time an interrupt request is activated, or when an interrupt request is cleared and others are max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 13 clear first irq, second irq still active second irq active first irq active clear irq single irq , intlevel = 1 posint = x intlevel = 0 posint = 0 intlevel = 0 posint = 1 clear last pending irq (1) width determined by time taken to clear the irq (2) 10.67 s (1) (2) int int int figure 10. behavior of the int pin for different intlevel and posint bit settings table 2. internal pullup resistor control connect vbgate vbus_det pullup 0 x x not connected 1 0 x connected 1 1 0 not connected 1 1 1 connected
max3420e pending (figure 10). set the posint bit in the pinctl (r17) register to make int active high, and clear the posint bit to make int active low. gpin3?pin0, gpout3?pout0 and gpx the max3420e has four general-purpose inputs (gpin3?pin0), four general-purpose outputs (gpout3?pout0), and a multiplexed output pin (gpx). gpin3 through gpin0 all have weak internal pullup resistors to v l . these inputs can be read by sampling bits 7 through 4 of the iopins (r20) register. writing to gpin3 through gpin0 has no effect. gpout3 through gpout0 are the general-purpose outputs. update these outputs by writing to bits 3 through 0 of the iopins (r20) register. gpout3 gpout0 logic levels are referenced to the voltage on v l . as shown in figure 11, reading the state of a gpout3?pout0 bit returns the state of the internal register bit, not the actual pin state. this is useful for doing read-modify-write operations to an output pin (such as blinking an led), since the load on the output pin does not affect the register logic state. gpx is a push-pull output with a 4-way multiplexer that selects its output signal. the logic level on gpx is refer- enced to v l . the spi master writes to the gpxb and gpxa bits of pinctl (r17) register to select one of four internal signals as depicted in table 3. operate: this signal goes high when the max3420e is able to operate after a power-up or res reset. operate is the default gpx output. vbus_det: vbus_det is the vbcomp comparator output. this allows the user to directly monitor the v bus status. busact: usb bus activity signal (active-high). this signal is active whenever there is traffic on the usb bus. the busact signal is set whenever a sync field is detected. busact goes low during bus reset or after 32-bit times of j-state. sof: a square wave with a positive edge that indicates the usb start-of-frame (figure 12). mosi (master-out, slave-in) and miso (master-in, slave-out) the spi data pins mosi and miso operate differently depending on the setting of a register bit called fdupspi (full-duplex spi). figure 13 shows the two configurations according to the fdupspi bit setting. usb peripheral controller with spi interface 14 ______________________________________________________________________________________ 14 ______________________________________________________________________________________ register bit gpout write gpout read gpout pin figure 11. behavior of read and write operations on gpout3?pout0 table 3. gpx output state gpxb gpxa gpx pin output 0 0 operate (default state) 0 1 vbus_det 1 0 busact 1 1 sof full-speed time frame 1ms full-speed time frame 1ms sof usb packets gpx sof sof ~50% figure 12. gpx output in sof mode fdupspi = 1 fdupspi = 0 (default) max3420e max3420e mosi miso mosi miso figure 13. max3420e spi data pins for full-duplex (top) and half-duplex (bottom) operation
in full-duplex mode (fdupspi = 1), the mosi and miso pins are separate, and the miso pin drives only when ss is low. in this mode, the first eight sclk edges (after ss = 0) clock the command byte into the max3420e on mosi, and eight usb status bits are clocked out of the max3420e on miso. for an spi write cycle, any bytes following the command byte are clocked into the max3420e on mosi, and zeros are clocked out on miso. for an spi read cycle, any bytes following the command byte are clocked out of the max3420e on miso and the data on mosi is ignored. at the conclusion of the spi cycle ( ss = 1), the miso output tri-states. in half-duplex mode, the mosi pin is a bidirectional pin and the miso pin is tri-stated. this saves a pin in the spi interface. because of the shared data pin, this mode does not offer the eight usb status bits (figure 5) as the command byte is clocked into the max3420e. the miso pin can be left unconnected in half-duplex mode. sclk (serial clock) the spi master provides the max3420e sclk signal to clock the spi interface. sclk has no low-frequency limit, and can be as high as 26mhz. the max3420e changes its output data (miso) on the falling edge of sclk and samples input data (mosi) on the rising edge of sclk. the max3420e ignores sclk transitions when ss is high. the inactive level of sclk may be low or high, depending on the spi operating mode (figure 14). ss (slave select) the max3420e spi interface is active only when ss is low. when ss is high, the max3420e tri-states the spi output pin and resets the internal max3420e spi logic. if ss goes high before a complete byte is clocked in, the byte-in-progress is discarded. the spi master can terminate an spi cycle after clocking in the first 8 bits (the command byte). this feature can be used in a full- duplex system to retrieve the usb status bits (figure 5) without sending or receiving spi data. applications information spi interface the max3420e operates as an spi slave device. a reg- ister access consists of the spi master first writing an spi command byte, followed by reading or writing the contents of the addressed register (see the register description section for more details). all spi transfers are msb first. the external spi master provides a clock signal to the max3420e sclk input. this clock fre- quency can be between dc and 26mhz. bit transfers occur on the positive edge of sclk. the max3420e counts bits and divides them into bytes. if fewer than 8 bits are clocked into the max3420e when ss goes high, the max3420e discards the partial byte. the max3420e spi interface operates without adjust- ment in either spi mode (cpol = 0, cpha = 0) or (cpol = 1, cpha = 1). no mode bit is required to select between the two modes since the interface uses the rising edge of the clock in both modes. the two clocking modes are illustrated in figure 14. note that the inactive sclk value is different for the two modes. figure 14 illustrates the full-duplex mode, where data is simultaneously clocked into and out of the max3420e. max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 15 ss miso mosi sclk mode 0,0 sclk mode 1,1 spi mode 0,0 or 1,1 *msb of next byte in burst mode (ss remains low) q7 q6 q5 q4 q3 d7 d6 d5 d4 d3 d2 d1 d0 * q2 q1 q0 * figure 14. spi clocking modes
max3420e spi half- and full-duplex operation the max3420e can be programmed to operate in half- duplex (a bidirectional data pin) or full-duplex (one data-in and one data-out pin) mode. the spi master sets a register bit called fdupspi (full-duplex spi) to 1 for full-duplex, and 0 for half-duplex operation. half- duplex is the power-on default. full-duplex operation when the spi master sets fdupspi = 1, the spi inter- face uses separate data pins, mosi and miso to trans- fer data. because of the separate data pins, bits can be simultaneously clocked into and out of the max3420e. the max3420e makes use of this feature by clocking out 8 usb status bits as the command byte is clocked in, as illustrated in figure 15. reading from the spi slave interface (miso) in full-duplex mode in full-duplex mode the spi master reads data from the max3420e slave interface using the following steps: (1) when ss is high, the max3420e is unselected and tri-states the miso output. (2) after driving sclk to its inactive state, the spi master selects the max3420e by driving ss low. the max3420e turns on its miso output buffer and places the first data bit (q7) on the miso output (figure 14). (3) the spi master simultaneously clocks the com- mand byte into the max3420e mosi pin, and usb status bits out of the max3420e miso pin on the rising edges of the sclk it supplies. the max3420e changes its miso output data on the falling edges of sclk. (4) after eight clock cycles, the master can drive ss high to deselect the max3420e, causing it to tri- state its miso output. the falling edge of the clock puts the msb of the next data byte in the sequence on the miso output (figure 14). (5) by keeping ss low, the master clocks register data bytes out of the max3420e by continuing to supply sclk pulses (burst mode). the master terminates the transfer by driving ss high. the master must ensure that sclk is in its inactive state at the beginning of the next access (when it drives ss low). in full-duplex mode, the max3420e ignores data on mosi while clocking data out on miso. writing to the spi slave interface (mosi) in full-duplex mode in full-duplex mode, the spi master writes data to the max3420e slave interface through the following steps: (1) the spi master sets the clock to its inactive state. while ss is high, the master can drive the mosi pin. (2) the spi master selects the max3420e by driving ss low and placing the first data bit to write on the mosi input. (3) the spi master simultaneously clocks the com- mand byte into the max3420e and usb status bits out of the max3420e miso pin on the rising edges of the sclk it supplies. the spi master changes its mosi input data on the falling edges of sclk. (4) after eight clock cycles, the master can drive ss high to deselect the max3420e. (5) by keeping ss low, the master clocks data bytes into the max3420e by continuing to supply sclk pulses (burst mode). the master terminates the transfer by driving ss high. the master must ensure that sclk is inactive at the beginning of the next access (when it drives ss low). in full-duplex mode, the max3420e outputs usb status bits on miso during the first 8 bits (the command byte), and sub- sequently outputs zeroes on miso as the spi mas- ter clocks bytes into mosi. half-duplex operation the max3420e is put into half-duplex mode at power- on, or when the spi master clears the fdupspi bit. in half-duplex mode, the max3420e tri-states its miso pin and makes the mosi pin bidirectional, saving a pin in the spi interface. the miso pin can be left unconnect- ed in half-duplex operation. because of the single data pin, the usb status bits available in full-duplex mode are not available as the spi master clocks in the command byte. in half-duplex mode these status bits are accessed in the normal way, as register bits. the spi master must operate the mosi pin as bidirec- tional. it accesses a max3420e register as follows: (1) the spi master sets the clock to its inactive state. while ss is high, the master can drive the mosi pin to any value. (2) the spi master selects the max3420e by driving ss low and placing the first data bit (msb) to write on the mosi input. (3) the spi master turns on its output driver and clocks the command byte into the max3420e on the rising edges of the sclk it supplies. the spi master changes its mosi data on the falling edges of sclk. (4) after eight clock cycles, the master can drive ss high to deselect the max3420e. usb peripheral controller with spi interface 16 ______________________________________________________________________________________
(5) to write spi data, the spi master keeps its output driver on and clocks subsequent bytes into the mosi pin. to read spi data, after the eighth clock cycle the spi master tri-states its output driver and begins clocking in data bytes from the mosi pin. (6) the spi master terminates the spi cycle by return- ing ss high. figures 8 and 9 show timing diagrams for full- and half- duplex operation. usb serial-interface engine the serial-interface engine (sie) does most of the detailed work required by usb protocol: usb packet pid detection and checking crc check and generation automatic retries in case of errors usb packet generation nrzi data encoding and decoding bit stuffing and unstuffing various usb error condition detection usb bus reset, suspend, and wake-up detection usb resume signaling automatic flow control (nak) pll an internal pll multiplies the 12mhz oscillator signal by four to produce an internal 48mhz clock. when the chip is powered down, the oscillator is turned off to conserve power. when repowered, the oscillator and pll require time to stabilize and lock. the oscokirq interrupt bit is used to indicate to the spi master that the clocking system is stable and ready for operation. power management according to usb rev. 2.0 specification, when a usb host stops sending traffic for at least 3 milliseconds to a peripheral, the peripheral must enter a power-down state called suspend. once suspended, the peripher- al must have enough of its internal logic active to rec- ognize when the host resumes signaling, or if enabled for remote wakeup, that the spi master wishes to signal a resume event. the following sections titled suspend and wakeup and usb resume describe how the spi master coordinates with the max3420e to accomplish this power management. suspend after three milliseconds of usb bus inactivity, a usb peripheral is required to enter the usb suspend state and draw no more than 500? of supply current. to accomplish this, after three milliseconds of usb bus inactivity, the max3420e sets the suspirq bit in the usbirq (r13) register and asserts the int output, if suspie = 1 and ie = 1. the spi master must do any necessary power-saving housekeeping and then set the pwrdown bit in the usbctl (r15) register. this instructs the max3420e to enter a power-down state, in which it does the following: stops the 12mhz oscillator keeps the int output active (according to the mode set in the pinctl (r17) register) monitors the usb d+ line for bus activity monitors the spi port for any traffic note that the max3420e does not automatically enter a power-down state after three milliseconds of bus inactivity. this allows the spi master to perform any max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 17 ss miso mosi sclk spi mode 0,0 (cpol = 0, cpha = 0) suspirq uresirq sudavirq in3bavirq in2bavirq reg4 reg3 reg2 reg1 reg0 0 dir ackstat out1davirq out0davirq in0bavirq x figure 15. spi port in full-duplex mode
max3420e preshutdown tasks before it requests the max3420e to enter the power-down state by setting pwrdown = 1. wakeup and usb resume the max3420e may wake up in three ways while it is in the power-down state: (1) the spi master clears the pwrdown bit in the usbctl (r15) register (this is also achieved by a chip reset). (2) the spi master signals a usb remote wakeup by setting the sigrwu bit in the usbctl (r15) regis- ter. when sigrwu = 1, the max3420e restarts the oscillator and waits for it to stabilize. after the oscil- lator stabilizes, the max3420e drives resume sig- naling (a 10ms k-state) on the bus. the max3420e times this interval to relieve the spi master of having to keep accurate time. the max3420e also ensures that the resume signal begins only after at least 5ms of the bus idle state. when the max3420e fin- ishes its resume signaling, it sets the rwudnirq (remote-wakeup-done interrupt request) interrupt flag in the usbirq (r13) register. at this time the spi master should clear the sigrwu bit. (3) the host resumes bus activity. to enable the max3420e to wake up from host signaling, the spi master sets the hoscsten (host oscillator start enable) bit of the usbctl (r15) register. while in this mode, if the max3420e detects a 1 to 0 transi- tion on d+, the max3420e restarts the oscillator and waits for it to stabilize. device reset the max3420e has three reset mechanisms: power-on reset. this is the most inclusive reset (sets all internal register bits to a known state). chip reset. the spi master can assert a chip reset by setting the bit chipres = 1, which has the same effect as pulling the res pin low. this reset clears only some register bits and leaves others alone. usb bus reset. a usb bus reset is the least inclusive (clears the smallest number of bits). power-on reset at power-on, all register bits except three are cleared. the following three bits are set to 1 to indicate that the in fifos are available for loading by the spi master (bav = buffer available): in3bavirq in2bavirq in0bavirq chip reset pulling the res pin low or setting chipres = 1 clears most of the bits that control usb operation, but keeps the spi and pin-control bits unchanged so the interface between the spi master and the max3420e is not dis- turbed. specifically: chipres is unchanged. if the spi master asserted this reset by setting chipres = 1, it removes the reset by writing chipres = 0. connect is unchanged, keeping the device connected if connect = 1. the general-purpose outputs gpout3?pout0 are unchanged, preventing output glitches. the gpx output selector (gpxb, gpxa) is unchanged. the bits that control the spi interface are unchanged: fdupspi, intlevel, and posint. the bits that control power-down and wakeup behavior are unchanged: hoscsten, pwrdown, and sigrwu. all other bits except the three noted in the power-on reset section are cleared. note: the irq and ie bits are cleared using this reset. this means that firmware routines that enable interrupts should be called after a reset of this type. usb bus reset when the max3420e detects 21.33? of se0, it asserts the uresirq bit and clears certain bits. this reset is the least inclusive of the three resets. it maintains the bit states listed in the power-on reset and chip reset sections, plus it leaves the following bits in their previ- ous states: registers r0?4 are unchanged. the actual data in the fifos is never cleared. the ie bit is unchanged. uresie, uresirq, uresdnie, and uresdnirq are unchanged, allowing the spi master to check the state of usb bus resets. as with the chip reset, most of the interrupt request and interrupt enable bits are cleared, meaning that the device firmware must reenable individual interrupts after a bus reset. the exceptions are the interrupts associat- ed with the actual bus reset, allowing the spi master to detect the beginning and end of the host signaling usb bus reset. usb peripheral controller with spi interface 18 ______________________________________________________________________________________
max3420e in a bus-powered application figure 16 depicts the max3420e in a peripheral device that is powered by v bus . this configuration is advanta- geous because it requires no external power supply. v bus is specified from 4.75v to 5.25v, so a 3.3v regu- lator is required to power the max3420e. this diagram assumes that the microprocessor is powered by 3.3v as well, so the v l pin (logic-level reference voltage) is connected to v cc . therefore, the gpio (general-pur- pose inputs/outputs) are referenced to 3.3v. usb is a hot-plug system (v bus is hot when the device is plugged in), so it is good design practice to use a power-on reset circuit to provide a clean reset to the system when the device is plugged in. the max6349tl serves as an excellent usb regulator, since it has very low quiescent current and a por circuit built in. because this design is bus powered, it is not necessary to test for the presence of v bus . in this case, the bus voltage-detection input, vbcomp, makes an excellent general-purpose input when pulled up to v l . the vbcomp input has two interrupts associated with it, vbusirq and novbusirq. these interrupts can detect both edges of any transitions on the vbcomp input. the configuration in figure 16 shows the spi interface using the maximum number of spi interface pins. the data pins, mosi and miso, are separate, and the max3420e supplies an interrupt signal through the int output pin to the ? to notify the ? when its attention is required. max3420e in a self-powered application figure 17 shows a self-powered design in which the ? has its own power source. this is a common configura- tion in battery-powered handheld devices. figure 17 also illustrates the spi interfacing with the minimum number of pins. this is achieved by using a single bidi- rectional data line and no interrupt pin connection. the max3420e register bit, fdupspi, configures the spi interface for bidirectional operation. although figure 17 shows v l = v cc , if the microcon- troller uses a different interface voltage (1.71v to 3.6v) this reference voltage can be connected to v l . figure 17 shows a connection from the max3420e gpx output to the microcontroller. gpx can be programmed (see table 3) to connect the output of the internal v bus comparator to the gpx output. this enables the microprocessor to detect a usb plug-in event even if the max3420e is put into its power-down state. max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 19 max3420e v cc v l xi xo int mosi miso sclk res d+ d- d+ d- vbcomp ss 0.1 f 10k gpi gnd v bus 33 33 1.0 f ceramic c xi c xo 12mhz 3.3v regulator max6349tl p 4 4 usb "b" connector gnd gpin gpout 4.7 f figure 16. max3420e in a bus-powered application
max3420e the v bus detect input, vbcomp, is an important max3420e feature. because the ? is powered whether the usb device is plugged in or not, it needs some way to detect a plug-in event. a comparator inside the max3420e checks for a valid v bus connec- tion on vbcomp and provides a connect status bit to the ?. once connected, the ? can delay the logical connection to the usb bus to perform any required ini- tialization, and then connect by setting the connect bit to 1 in the max3420e register usbctl (r15). this connects the internal 1.5k resistor from d+ to v cc , to signal the host that a device has been plugged in. if a host turns off v bus while the device is connected, the usb rev. 2.0 specification requires that the device must not power its 1.5k pullup resistor connected to d+. the max3420e has two features to help service this event. first, the novbusirq bit indicates the loss of v bus . second, the ? can set a bit called vbgate (v bus gate) to instruct the max3420e to disconnect the pullup resistor anytime v bus goes away, regardless of the connect bit setting. crystal selection the max3420e requires a crystal with the following specifications: frequency: 12mhz 0.25% c load : 18pf c o : 7pf max drive level: 200? series resonance resistance: 60 max note: series resonance resistance is the resistance observed when the resonator is in the series resonant condition. this is a parameter often stated by quartz crys- tal vendors and is called r1. when a resonator is used in the parallel resonant mode with an external load capaci- tance, as is the case with the max3420e oscillator circuit, the effective resistance is sometimes stated. this effec- tive resistance at the loaded frequency of oscillation is: r1 x ( 1 + (c o / c load )) 2 for typical c o and c load values, the effective resis- tance can be greater than r1 by a factor of 2. usb peripheral controller with spi interface 20 ______________________________________________________________________________________ max3420e v cc v l xi xo n.c. n.c. int mosi gpx miso sclk res d+ d- d+ d- vbcomp ss 0.1 f gnd gnd gpin gpio gpout v bus 33 33 1.0 f ceramic 1.0 f ceramic c xi c xo 12mhz p 4 4 usb "b" connector +3.3v figure 17. max3420e in a self-powered application
esd protection d+, d-, and vbcomp possess extra protection against static electricity to protect the devices up to ?5kv. the esd structures withstand high esd in all operating modes: normal operation, suspend mode, and pow- ered down. vbcomp and v cc require 1? ceramic capacitors connected to ground as close to the pins as possible. d+, d-, and vbcomp provide protection to the following limits: ? ?5kv using the human body model ? ?kv using the contact discharge method specified in iec 61000-4-2 ? ?2kv using the iec 61000-4-2 air gap method esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 18 shows the human body model, and figure 19 shows the current waveform generated when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which then discharges into the test device through a 1.5k resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. it does not specifi- cally refer to integrated circuits. the major difference between tests done using the human body model and iec 61000-4-2 is a higher peak current in iec 61000-4- 2, due to lower series resistance. hence, the esd with- stand voltage measured to iec 61000-4-2 generally is lower than that measured using the human body model. figure 20 shows the iec 61000-4-2 model. the contact discharge method connects the probe to the device before the probe is charged. the air-gap discharge test involves approaching the device with a charged probe. short-circuit protection the max3420e withstands v bus shorts to d+ and d- on the usb connector side of the 33 series resistors. chip information process: bicmos max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 21 figure 19. human body model current waveform i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 18. human body esd test models charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 20. iec 61000-4-2 esd test model charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test
max3420e usb peripheral controller with spi interface 22 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
max3420e usb peripheral controller with spi interface ______________________________________________________________________________________ 23 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
max3420e usb peripheral controller with spi interface 24 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32l/48l,lqfp.eps f 1 2 21-0054 package outline, 32/48l lqfp, 7x7x1.4mm
max3420e usb peripheral controller with spi interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history pages changed at rev 2: 4, 5, 19, 20, 22, 23, 24, 25 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) f 2 2 21-0054 package outline, 32/48l lqfp, 7x7x1.4mm

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